I have a few veriloga based subcircuits to implement an A/D converter which function as desired for a transient simulation when the input signal signal VIN changes value as a function of time. Parameter real vlogic_low = 0.0 from [0:inf) ![]() ![]() Parameter real vlogic_high = 0.6 from [0:inf) Is there any way to trigger an analog event at any change on a given voltage? (in this case V(in)) ![]() To make it work for a transient simulation I would need an analog event to check at any change in V(Vin) (voltage at Vin net), while I am aware only of "cross" or "above" functions to use in the sensitivity, and of course it isn't practical to define the all 2^bits number of thresholds V(in) might cross. I could do this with the code shown below, but that works only for a DC simulation, because the forces the model to calculate the output at the beginning of the simulation. Basically I would like to give an input Vin via vdc voltage source and get it converted to an output bus of N nets being the binary representation.įor example if Vin net has a voltage of 5V and the model has 4 bits, then the output bus will be out with out=0,Vdd,0,Vdd. I am trxing to create a VerilogA model of a decimal to binary converter.
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